Efficient Design of Nano Scale Adder and Subtractor Circuits using Quantum dot Cellular Automata

Low power dissipation, high packaging density and operation at Tera-hertz frequencies are highly desired features in the design and fabrication of logic circuits. Promising realization of these highly desired features have made Quantum dot Cellular Automata (QCA) a prospective replacement to the conventional CMOS technology for the fabrication of logic circuits in nano scale range. The traditional technologies including CMOS use voltage levels to represent binary states, whereas Quantum dot Cellular Automata uses polarization of electrons to represent binary states. In any arithmetic design, modulo-2 addition is required and most suitable gate for obtaining this function is an XOR gate. An efficient XOR gate can facilitate the design of arithmetic circuits with less number of cells and thus can save area of occupation on the chip. This paper proposes various designs for adder and subtractor circuits in QCA that require reduced number of cells and therefore can save chip area to a larger extent. The proposed design is suitable for applications in arithmetic systems in nano scale range. The experimentation with the proposed designs have been successfully verified through the QCADesigner tool.